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Integrated Circuit Systems, Inc.
ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: * Low skew, low jitter PLL clock driver * I2C for functional and output control * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * 3.3V tolerant CLK_INT input Switching Characteristics: * PEAK - PEAK jitter (66MHz): <120ps * PEAK - PEAK jitter (>100MHz): <75ps * CYCLE - CYCLE jitter (66MHz):<110ps * CYCLE - CYCLE jitter (>100MHz):<65ps * OUTPUT - OUTPUT skew: <100ps * Output Rise and Fall Time: 650ps - 950ps * DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLK_INT N/C VDDA GND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA N/C FB_INT FB_OUTT N/C CLKT3 CLKC3 GND
28-Pin SSOP
Block Diagram
Functionality
INPUTS AVDD
FB_OUTT
OUTPUTS CLKT CLKC FB_OUTT L H Z H L Z L H Z
ICS93722
CLK_INT L H <20MHz
PLL State on on off
2.5V (nom) 2.5V (nom) 2.5V (nom)
SCLK SDATA
Control Logic
CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2
FB_INT PLL CLK_INT
CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5
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ICS93722
Pin Descriptions
PIN NUMBER 6, 11, 15, 28 PIN NAME GND TYPE PWR OUT OUT PWR Ground "Complementar y" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs. Power supply 2.5V DESCRIPTION
27, 25, 16, 14, 5, 1 CLKC(5:0) 26, 24, 17, 13, 4, 2 CLKT(5:0) 3, 12, 23 7 8 9, 18, 21 10 19 20 22 VDD
SCLK
CLK_INT N/C VDDA FB_OUTT FB_INT
IN
IN PWR OUT IN
Clock input of I2C input, 5V tolerant input
"True" reference clock input Not connected Analog power supply, 2.5V "True" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error.
SDATA
IN
Data input for I2C serial input, 5V tolerant input
Bytes 0 to 4 are reserved power up default = 1. Byte 5: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 2, 1 4, 5 13, 14 17, 16 PWD 1 1 1 1 1 1 1 1 DESCRIPTION CLK0 (T&C) Reserved Reserved Reserved CLK2 (T&C) CLK3 (T&C) Reserved Reserved
Byte 6: Output Control (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIN# 24, 25 26, 27 PWD 1 1 1 1 1 1 1 1 DESCRIPTION Reser ved Reser ved Reser ved Reser ved CLK4 (T&C) Reser ved CLK5 (T&C) Reser ved
Note: PWD = Power Up Default
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ICS93722
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND -0.5 V to VDD +0.5 V 0C to +85C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output High Current High Impedance Output Current Input Clamp Voltage High-level Output Voltage Low-level Output Voltage Input Capacitance
1 1
SYMBOL IIH IIL IDD2.5 IDDPD IOH IOL IOZ VIK VOH VOL CIN COUT
CONDITIONS VIN = VDD or GND VIN = VDD or GND CL = 0 pF at 133 MHz CL = 0 pF VDD = 2.3V, VOUT = 1V VDD = 2.3V, VOUT = 1.2V VDD = 2.7V, VOUT = VDD or GND IIN = -18 mA; VDD = min to max, IOH = -1mA VDD = 2.3V, IOH = -12mA VDD = min to max, IOH = 1mA VDD = 2.3V, IOH = 12mA VIN = VDD or GND VOUT = VDD or GND
MIN
TYP
MAX
UNITS A A
275 -43 26 43
325 100 -18
mA A mA mA
10
A V
2.1
2.42 1.87 0.04 0.35 3 0.1 0.6
V V V V pF pF
Output Capacitance
1. Guaranteed by design, not 100% tested in production.
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ICS93722
Recommended Operating Conditions
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Analog / Core Supply Voltage Input Voltage Level Inpu Duty Cycle Input max jitter SYMBOL VDD, AVDD VIL VIH IDC ITCYC VDD/2 + 0.5V 40 60 500 ps CONDITIONS MIN 2.3 TYP 2.5 MAX 2.7 VDD/2 - 0.5V UNITS V V V
Timing Requirements
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Operating Clock Frequency Input Clock Duty Cycle Clock Stabilization
1 1 1
SYMBOL freqop dtin tSTAB
CONDITIONS
MIN 66 40
TYP
MAX 200 60 100
UNITS MHz % s
from VDD = 2.5V to 1% target frequency
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Absolute Jitter1 Cycle to cycle Jitter1,2 Phase Error Pulse Skew
1 1
SYMBOL Tjabs Tcyc-cyc t(phase error) Tskew Tskewp DC tR, tF
CONDITIONS 66 MHz 100 - 200 MHz 66 MHz 100 - 200 MHz CLK_INT to FB_INT VT = 50% VT = 50%, 66 MHz to 100 MHz VT = 50%, 101 MHz to 167 MHz Single-ended 20 - 80 % Load = 120 / 12 pF
MIN
TYP
MAX 120 75
UNITS ps ps ps ps ps % ps
50 25 -150 50 70 49.5 49 450 50 50 550
110 65 150 100 100 50.5 51 950
Output to output Skew
1
Duty Cycle (differential)1,3 Rise Time, Fall Time
1
1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting output. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.
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ICS93722
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controlle r (Host) Start Bit Address D4 (H ) Dummy Command Code ICS (Sla ve /Re ce ive r)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controlle r (Host) Start Bit Address D5(H ) ICS (Sla ve /Re ce ive r)
A CK A CK
Dummy Byte Count
A CK Byte Count
ACK
Byte 0
A CK
ACK
Byte 0
Byte 1
A CK
ACK
Byte 1
Byte 2
A CK
ACK
Byte 2
Byte 3
A CK
ACK
Byte 3
Byte 4
A CK
ACK
Byte 4
Byte 5
A CK
ACK
Byte 5
Byte 6
A CK
ACK Stop Bit
Byte 6
A CK
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS93722
N
c
SYMBOL
L
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 1.65 0.22 2.00 1.85 0.38 .002 .065 .009 .079 .073 .015
A A1 A2 b c D E
INDEX AREA
E1
E
0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0 8
.0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0 8
12 D
A2 A1
A
E1 e L N
-Ce
b SEATING PLANE .10 (.004) C
VARIATIONS N 28 D mm. MIN 9.90 MAX 10.50 MIN .390
MO-150 JEDEC Doc.# 10-0033
D (inch) MAX .413
6/1/00 Rev B
209 mil SSOP
Ordering Information
ICS93722yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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